8 or 16 bit access in non-cacheable GC RAM
Posted: Sun Dec 11, 2011 5:22 pm
Dear all,
I would like some feedback on a issue i have.
In GC memory model given by devkitpro examples, the CPU can access its RAM by a cacheable way at address 0x80000000 but also by a non-cacheable way at address 0xC0000000.
For this ,i am OK.
But if a program executes load and store 32bit word (stw, lwz) at address 0xC000XXXX it works.
But if a programm executes load or store 8bit (lwb, stb) at address 0xC000XXXX, it crash.
It seems that the RAM of GC support only burst access from cache and 32bit access but not 8 or 16 bit access .
Tell me if i am right ?
And i do not find any of this hardware behaviour in the YAGCD ?
Can you help me, please ?
Regards.
I would like some feedback on a issue i have.
In GC memory model given by devkitpro examples, the CPU can access its RAM by a cacheable way at address 0x80000000 but also by a non-cacheable way at address 0xC0000000.
For this ,i am OK.
But if a program executes load and store 32bit word (stw, lwz) at address 0xC000XXXX it works.
But if a programm executes load or store 8bit (lwb, stb) at address 0xC000XXXX, it crash.
It seems that the RAM of GC support only burst access from cache and 32bit access but not 8 or 16 bit access .
Tell me if i am right ?
And i do not find any of this hardware behaviour in the YAGCD ?
Can you help me, please ?
Regards.