I'm using a custom board which has an ARMv7 device with separate L1 caches for instructions and data. The code generated by GCC places literal pools after each function and loads the constants using 'ldr' and an offset from the pc. I would like to force GCC to place all the literal pools in the data segment and not in the text segment since I want to test the performance of the data cache, not the instruction cache. This option is possible for Xtensa targets but not GCC...
In short, I need to disable loading data from the text segment and place all data in the data segment in a kind of Harvard architecture... Any hints ?
support for the ARM toolchain
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